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SP5668 2.7ghz 3-wire bus controlled synthesiser preliminary information ds4538 issue 1.6 january 1997 ordering information SP5668/kg/mp1s (tubes) SP5668/kg/mp1t tape and reel) the SP5668 is a single chip frequency synthesiser designed for tuning systems up to 2.7ghz. the rf preamplifer contains a divide by two prescaler which can be disabled for applications up to 2ghz so enabling a step size equal to the comparison frequency up to 2ghz and twice the comparison frequency up to 2.7ghz. comparison frequencies are obtained either from a crystal controlled on?hip oscillator or from an external source. the device contains three switching ports, p0 ?p2, together with an ?n?ock?flag output. various test modes including varactor disable and charge pump disable are also included. features complete 2.7ghz single chip system optimised for low phase noise selectable divide by two prescaler selectable reference division ratio charge pump disable varactor line disable ?n?ock?flag two selectable charge pump currents three switching ports reference frequency output esd protection (normal esd handling procedures should be observed) applications sat, tv, vcr and cable tuning systems communications systems figure 1 - pin connections - top view mp16 charge pump cap q1 crystal q2 enable data clock port p2 port p1/oc drive v ee rf input rf input v cc lock ref port p0/oc
2 SP5668 preliminary information reference divider see table 1 de 13 14 inputs rf programmable divider 16/17 2/1 4 bit count 13 bit count f pd f comp phase comp charge pump osc f ref ref crystal q1 crystal q2 charge pump drive 1 16 os co lock 1 bit latch 3 bit latch (r0,r1,r2) 1 bit latch flock 1 bit latch 3 bit latch and port interface data interface disable 18 bit latch enable clock data 4 5 6 p2 p1 p0 figure 2 - SP5668 block diagram electrical characteristics t amb = 120 c to +80 c, v cc = +4.5 to +5.5v. reference frequency = 4mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. characteristic pin value units conditions min typ max supply current, icc 12 65 81 ma vcc = 5v prescaler enabled, pe = 1 58 72 ma vcc = 5v prescaler disabled, pe = 0 rf input voltage 13, 14 100 300 mv rms 100mhz prescaler enabled, pe = 1 see fig. 5b. 13, 14 40 300 mv rms 300mhz - 2.7ghz prescaler enabled, pe = 1, see fig. 5b. 13,14 40 300 mv rms 100mhz to 2.0ghz prescaler disabled, pe = 0, see fig. 5a rf input impedance 13, 14 see fig. 4. data, clock, enable 4,5,6 input high voltage 3 v cc v input low voltage 0 0.7 v input high current 10 a input voltage = v cc input low current -10 a input voltage = v ee hysteresis 400 mv clock rate 6 500 khz
3 SP5668 electrical characteristics (continued) t amb = 120 c to +80 c, v cc = +4.5 to +5.5v. reference frequency = 4mhz. these characteristics are guaranteed by either production test or design. they apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. characteristic pin value units conditions min typ max bus timing 4, 5, 6 data set up , t su 300 ns see fig. 3 data hold, t hd 600 ns see fig. 3 enable set up, t es 300 ns see fig. 3 enable hold , t eh 600 ns see fig. 3 clock to enable, t ce 300 ns see fig. 3 charge pump output 1 see table 3, v pin1 =2v current charge pump output 1 10 na v pin1 = 2v leakage drive output current 16 1 ma v pin16 = 0.7v drive output saturation 16 350 mv os = 1 voltage when disabled external reference input 3 2 20 mhz ac coupled sinewave frequency external reference input 3 200 500 mvp-p ac coupled sinewave amplitude crystal frequency 3 4 12 mhz recommended crystal 10 200 ? applies to 4mhz crystal only. series resistance "parallel resonant" crystal. figure quoted is under all conditions including start up. reference oscillator bias 3 200 a see fig. 11 current ref output voltage* 10 350 mvp-p ac coupled, 4mhz reference frequency, see fig. phase detector comparison 4 mhz frequency equivalent phase noise at dbc/hz see **note phase detector rf division ratio 240 131071 pe = 0, prescaler disabled 480 262142 pe = 1, prescaler enabled reference division ratio see table 1 output ports p0-p2 7-9 sink current 10 ma v port = 0.7v leakage current 10 av port = 13.2v lock output sink current 1 ma v pin10 = 0.7v, 'out of lock' leakage current 10 a 'in lock' * ref output should be connected to v cc if unused ** note: 1. -148dbc/hz @ 1khz offset with 1mhz comparison frequency measured at the phase comparator. 2. when external reference is used, a high signal level is required for low phase noise.
4 SP5668 preliminary information absolute maximum ratings all voltages are referred to v ee at 0v charateristics pin min max units conditions supply voltage, v cc 12 -0.3 7 v rf input voltage 13, 14 2.5 vp-p rf input offset 13, 14 -0.3 v cc +0.3 v port output voltage 7-9 -0.3 14 v port in off state 7-9 -0.3 6 v port in on state total port current 7-9 50 ma refoutput dc offset 10 -0.3 v cc +0.3 v lock output dc offset 11 -0.3 v cc +0.3 v lock output current 11 10 ma charge pump dc offset 1 -0.3 v cc +0.3 v drive dc offset 16 -0.3 v cc +0.3 v crystal oscillator dc offset 2, 3 -0.3 v cc +0.3 v data, clock & inputs 4,5,6 -0.3 v cc +0.3 v storage temperature -55 +150 c junction temperature +150 c mp16 thermal resistance chip to ambient 111 c/w chip to case 41 c/w power consumption 407 mv all ports off, prescaler enabled at v cc = 5.5v esd protection all 2 kv mil-std 883 tm3015 functional description the SP5668 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscil- lator, so forming a complete pll frequency synthesised source. the device allows for operation with a high compari- son frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. the rf preamplifier contains a selectable di- vide by two for operation above 2.0ghz. up to 2ghz the rf input interfaces directly with the programmable divider, so eliminating degradation in phase noise due to the prescaler action. the block diagram is shown in fig.2. the SP5668 is controlled by a standard 3 wire bus com- prising data, clock and enable inputs. the programming word contains 27 bits. p0 - p2 are used for port selection, 2 17 - 2 0 set the programmable divider ratio r2 - r0 select the reference division ratio (table1). c0 sets the charge pump current (table 3) and the remaining two bits t0, os access test modes and disable the varactor drive (table 2).the programming format is shown in fig. 3. the clock input is disabled by an enable low signal, data is therefore only clocked into the internal shift registers during an enable high and is loaded into the controlling buffers by an enable high to low transition. this load is also synchronised with the programmable divider so giving smooth fine tuning. the rf signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. the output of the preamplifier is fed to the 2/1 selectable prescaler and then to the 17 bit fully programmable divider, which is of mn+a architecture. the m counter is 13 bit and the a counter 4. if bit pe is set to a 0 the prescaler is disabled; the control function pe cannot be used dynamically. the output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. this frequency is derived either from the on board crystal controlled oscillator or from an external source. in both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 8 ratios as described in table 1. the output of the phase comparator feeds the charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter integrates the current pulses into the varactor line voltage. the charge pump current is selected by bit c0 as described in table 3. the phase comparator also drives the lock detect circuit which generates a lock flag. 'in-lock' is indicated by a high impedance state on the lock output. the crystal frequency fref is available at the ref output. this may be used as the reference for a second synthesiser as shown in fig. 6. the ref output is disabled by connecting the output, pin 3, to v cc .
5 SP5668 figure 3 - data format and timing phase noise the SP5668 has been designed to offer good phase noise performance even when operated with a standard low profile 4mhz crystal and a high comparison frequency, e.g. 2mhz. the typical phase noise performance measured in the standard application is contained in table 4. it has been demonstrated that even higher levels of performance will be achieved in a tuner application. test modes the programmable divider output divided by two fpd/2 and the comparison frequency fcomp, can be switched to ports p0 and p1 respectively. the charge pump can be forced to either source or sink current, and may be disabled to high impedance state. the varactor drive output can be disabled by the os bit within the data word, so switching the external transistor 'off' and allowing an external voltage to be written to the varactor line for tuner alignment purposes. the test modes are described in table 2. clock enable data frequency data 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 2 0 p2 p1 p0 to os co r2 r1 r0 pe lsb 2 16 to 2 0 t : programmable divider ratio control bits r2 r1 r0 ,, t : reference divider ratio control bits (see t able 1) p2, p1, p0 t : port control bits co t : charge pump current select (see t able 3) os t : drive output disable switch t0 t : t est mode enable (see t able 2) msb pe : 2 prescaler (enable = 1, disable = 0) r2 r1 r0 ratio comparison frequency with a 4mhz external reference 0002 2mhz 0014 1mhz 0108 500khz 0 1 1 16 250khz 1 0 0 32 125khz 1 0 1 64 62.5khz 1 1 0 128 31.25khz 1 1 1 256 15.625khz table 1 - reference division ratio p1 p0 t0 functional description x x 0 normal operation 0 0 1 charge pump sink. lock output = lo z 0 1 1 charge pump source. lock output = hi z 1 0 1 charge pump disable. lock output = lo z 1 1 1 port p1 = fcomp: port 0 = fpd/2 x = don't care table 2 - test modes
6 SP5668 preliminary information c0 current in ma min typ max 0 0.23 0.30 0.37 1 0.68 0.90 1.12 table 3 - charge pump f lo f comp rf division vco phase equivalent (4mhz xtal) ratio noise @1khz phase noise offset (dbc/hz) phase detector (dbc/hz) 2ghz 1mhz 2000 -84 -146 2ghz 2mhz 1000 -80 -144 table 4 - typical phase noise figure 4 - typical input impedance 0.5 0.2 1 0 +j0.2 +j0.5 +j1 +j2 +j5 2 5 j5 j2 j1 j0.5 j0.2 frequency markers a t 100mhz, s 11 :z 0 = 50 x x x x normalised t o 50 ? 500mhz, 1ghz and 2.7ghz
7 SP5668 vco vco 10nf 50 - 900mhz 38.9mhz 1650-2700mhz 2 3 10 3 SP5668 SP5668 1.6ghz figure 5a - typical input sensitivity (prescaler disabled, pe=0) figure 6 - example of double conversion from vhf/uhf frequencies to tv if figure 5b - typical input sensitivity (prescaler enabled, pe=1) 300 100 40 10 1000 2000 3000 frequency (mhz) 3500 operating window 1000 2000 2700 3000 frequency (mhz) 3500 300 operating window 300 100 40 10 vin (mv rms int o 50 ? ) vin (mv rms int o 50 ? ) 100 80 80 50 figure 7 - typical application, SP5668 control micro 15nf 68pf +30v +5v 22k 16k 47k +12v 2n2 bcw31 1n 1n 10n p2 tuner oscillator output SP5668 13k3 p0 lock clock data enable optional application utilising on?oard crystal controlled oscillator 1 14 2 3 4 5 6 7 13 12 11 10 89 15 16 p1 4mhz 18pf 2 3 39pf reference
8 SP5668 preliminary information 1 14 external reference skt2 10nf *(not fitted) c7 c2 15nf r6 13k3 c3 68pf +5v p2 +12v c10 c9 100nf r2 22k c1 1 100nf r9 16k r10 c14 2n2f var gnd t1 bcw31 13 12 11 10 9 8 2 3 4 5 6 7 c3 1nf c5 1nf skt1 rf input c4 10nf r5 4k7 d5 d4 d2 d1 r4 4k7 r7 4k7 r6 4k7 c6 18pf x1 4mhz p1 c12 100pf c13 100pf enable data / sda clock / scl 8 +30v pin no : 7 lock c8 39pf 15 16 reference output skt sw1 100nf 47 f 47 f 47k sw2 lock p0 p1 p2 application notes a generic set of application notes an168 for designing with synthesisers such as the SP5668 has been written. this covers aspects such as loop filter design and decoupling. this application note is also featured in the media ic handbook. a generic test/demo board has been produced which can be used for the SP5668. a circuit diagram is shown in fig. 8. the board can be used for the following purposes: (a) measuring rf sensitivity performance. (b) indicating port function (c) synthesising a voltage controlled oscillator (d) testing of external reference sources figure 8 - evaluation board
9 SP5668 loop bandwidth the majority of applications for which the SP5668 is intended require a loop filter bandwidth of between 2khz and 10khz. typically the vco phase noise will be specified at both 1khz and10khz offset. it is common practice to arrange the loop filter bandwidth such that the 1khz figure lies within the loop bandwidth. thus the phase noise depends on the synthesiser comparator noise floor, rather than the vco. the 10khz offset figure should depend on the vco providing the loop is designed correctly, and is not underdamped. reference source the SP5668 offers optimal lo phase noise performance when operated with a large step size. this is due to the fact that the lo phase noise within the loop bandwidth is: phase comparator noise floor + 20 log assuming the phase comparator noise floor is flat irrespective of sampling frequency, this means that the best performance will be achieved when the overall lo to phase comparator division ratio is a minimum. there are two ways of achieving a higher phase comparator sampling frequency: a) reduce the division ratio between the reference source and the phase comparator b) use a higher reference source frequency. approach b) may be preferred for best performance since it is possible that the noise floor of the reference oscillator may degrade the phase comparator performance if the reference division ratio is very small. lo frequency phase comparator frequency ()
10 SP5668 preliminary information v ref 500 500 rf inputs v cc charge pump drive output port/lock xtal rf inputs loop amplifier disable, enable, data and clock inputs reference oscillator output ports and lock output v cc bias 25k 200 os (output disable) v cc cap reference output v cc 1.2ma ref figure 9 - input/output interface circuits

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